Ninth International Workshop on
Programmability and Architectures for Heterogeneous Multicores
(MULTIPROG-2016)
To be held in conjunction with:
the 11th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC)
Prague, Czech Republic, January 18, 2016
Computer manufacturers have embarked on the many-core roadmap, promising to add more and more cores/hardware threads on their chips. The ever-increasing number of cores and heterogeneity in architectures has placed new burdens on the programming community. Software needs to be parallelized and optimized for accelerators such as GPUs in order to take advantage of the new breed of multi-/many-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.
The ninth edition of the MULTIPROG workshop aims to bring together researchers interested in programming models, runtimes, and computer architecture. The workshop's emphasis is on heterogeneous architectures and covers issues such as:
- How can future parallel programming models improve software productivity?
- How should compilers, runtimes and architectures support programming models and emerging applications?
- How to design efficient data structures and innovative algorithms?
MULTIPROG is intended for quick publication of early results, work-in-progress, etc., and is not intended to prevent later publication of extended papers. Informal proceedings with accepted papers will be made available at the workshop and online at the workshop’s web page http://research.ac.upc.edu/multiprog/.
Topics of interest
Papers are sought on topics including, but not limited to:
- Multi-core architectures
- Architectural support for compilers/programming models
- Processor (core) architecture and accelerators, in particular GPUs
- Memory system architecture
- Performance, power, temperature, and reliability issues
- Heterogeneous computing
- Algorithms and data structures for heterogeneous systems
- Applications for heterogeneous computing and real-time graphics
- Programming models for multi-core architectures
- Language extensions
- Run-time systems
- Compiler optimizations and techniques
- Benchmarking of multi-/many-core architectures
- Tools for discovering and understanding parallelism
- Tools for understanding performance and debugging
- Case studies and performance evaluation
Program
Download the informal proceedings of the MULTIPROG'2016 Workshop
10:00 Welcome and Keynote
Welcome (15 min)MULTIPROG organizers.
Keynote: David Kaeli (Northeastern University)
Title: Accelerators as First-class Computing Devices (45 min)
11:30 Architectures and Execution Models
Invited talk: Per Stenström (Chalmers University of Technology)Title: MECCA - Meeting the Challenges in Computer Architecture (30 min)
Accelerating HPC Kernels with RHyMe - REDEFINE HyperCell Multicore (20 min)
Saptarsi Das, Nalesh S., Kavitha Madhu, Soumitra Kumar Nandy and Ranjani Narayan
An Execution Model for OpenCL 2.0 (20 min)
Benedict Gaster
Project Beehive: A Hardware/Software Co-designed Stack for Runtime and Architectural Research (10 min short presentation)
Christos Kotselidis, Andrey Rodchenko, Colin Barrett, Andy Nisbet, John Mawer, Will Toms, James Clarkson, Cosmin Gorgovan, Amanieu d'Antras, Yaman Cakmakci, Thanos Stratikopoulos, Sebatian Werner, Jim Garside, Javier Navaridas, Antoniu Pop, John Goodacre and Mikel Lujan
Reaching intrinsic compute efficiency requires adaptable micro-architectures (10 min short presentation)
Mark Wijtvliet, Luc Waeijen, Michaël Adriaansen and Henk Corporaal
14:00 Programming Models
Invited talk: Rainer Leupers (Silexica Software Solutions GmbH)Title: Use Case Driven Embedded Multicore Software Development (30 min)
Toward Transparent Heterogeneous Systems(20 min)
Baptiste Delporte, Roberto Rigamonti and Alberto Dassatti
Exploring LLVM Infrastructure for Simplified Multi-GPU Programming (20 min)
Alexander Matz, Mark Hummel and Holger Fröning
Efficient scheduling policies for dynamic dataflow programs executed on multi-core (10 min short presentation)
Malgorzata Michalska, Nicolas Zufferey, Jani Boutellier, Endri Bezati and Marco Mattavelli
OpenMP scheduling on ARM big.LITTLE architecture (10 min short presentation)
Anastasiia Butko, Louisa Bessad, David Novo, Florent Bruguier, Abdoulaye Gamatie, Gilles Sassatelli, Lionel Torres and Michel Robert
16:00 Applications and Benchmarking
Invited talk: Jean-Francois Lavignon (European Technology Platform for High Performance Computing (ETP4HPC))Title: The ETP4HPC Strategic Research Agenda (30 min)
Collaborative design and optimization using Collective Knowledge (20 min)
Anton Lokhmotov and Grigori Fursin
Heterogeneous (CPU+GPU) Working-set Hash Tables (20 min)
Ziaul Choudhury and Suresh Purini
A Safe and Tight Estimation of the Worst-Case Execution Time of Dynamically Scheduled Parallel Applications (10 min short presentation)
Petros Voudouris, Per Stenström and Risat Pathan
Important dates
| Full paper submission: | Extended until November 22, 2015 (anywhere on Earth). November 6, 2015 |
| Notification to authors: | December 11, 2015 December 4, 2015 |
Paper Submission
MULTIPROG is now accepting contributions of regular research papers and short position papers describing early research on emerging topics. When preparing your submission please adhere to the following format specification:
- Regular research papers: Regular research papers should preferably use LNCS format (up to 12 pages, not including references). Single column (up to 12-Pages) or double column (up to 6-pages) formats are also accepted.
- Short position papers: Short position papers should preferably use LNCS format (4-6 pages, not including references). Single column (4-6 pages) or double column (2-3 pages) formats are alsoaccepted. Papers in this category should explicitly indicate "Position Paper" as part of the title of their manuscript.
- LNCS Latex template: ftp://ftp.springer.de/pub/tex/latex/llncs/latex2e/llncs2e.zip
- Word template: ftp://ftp.springer.de/pub/tex/latex/llncs/word/splnproc1110.zip
Submission link: https://easychair.org/conferences/?conf=multiprog2016
Organizers
| Miquel Pericàs | Chalmers University of Technology | Sweden | miquelp[at]chalmers.se |
| Vassilis Papaefstathiou | Chalmers University of Technology | Sweden | vaspap[at]chalmers.se |
| Oscar Palomar | Barcelona Supercomputing Center | Spain | oscar.palomar[at]bsc.es |
| Ferad Zyulkyarov | Barcelona Supercomputing Center | Spain | ferad.zyulkyarov[at]bsc.es |
Steering committee
| Eduard Ayguade | UPC/Barcelona Supercomputing Center | Spain | eduard[at]ac.upc.edu |
| Benedict R. Gaster | Qualcomm | USA | bgaster[at]qti.qualcomm.com |
| Lee Howes | Qualcomm | USA | lhowes[at]qti.qualcomm.com |
| Per Stenstrom | Chalmers University of Technology | Sweden | pers[at]chalmers.se |
| Osman Unsal | BSC-Microsoft Research Centre | Spain | osman.unsal[at]bsc.es |
Program committee
| Abdelhalim Amer | Argonne National Lab | USA |
| Ali Jannesari | TU Darmstadt | Germany |
| Avi Mendelson | Technion | Israel |
| Christos Kotselidis | University of Manchester | UK |
| Daniel Goodman | Oracle Labs | UK |
| Dong Ping Zhang | AMD | USA |
| Gilles Sassatelli | LIRMM | France |
| Håkan Grahn | Blekinge Institute of Technology | Sweden |
| Hans Vandierendonck | Queen's University of Belfast | UK |
| Kenjiro Taura | University of Tokyo | Japan |
| Luigi Nardi | Imperial College London | UK |
| Naoya Maruyama | RIKEN AICS | Japan |
| Oscar Plata | University of Malaga | Spain |
| Pedro Trancoso | University of Cyprus | Cyprus |
| Polyvios Pratikakis | FORTH-ICS | Greece |
| Roberto Gioiosa | Pacific Northwest National Laboratory | USA |
| Ruben Titos | BSC | Spain |
| Sasa Tomic | IBM Research | Switzerland |
| Simon McIntosh-Smith | University of Bristol | UK |
| Timothy G. Mattson | Intel | USA |
| Trevor E. Carlson | Uppsala University | Sweden |
Webmaster: ferad.zyulkyarov[at]bsc.es