Tenth International Workshop on
Programmability and Architectures for Heterogeneous Multicores
To be held in conjunction with:
the 12th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC)
Stockholm, Sweden, January 24, 2017
Computer manufacturers have embarked on the many-core roadmap, promising to add more and more cores/hardware threads on their chips. The ever-increasing number of cores and heterogeneity in architectures has placed new burdens on the programming community. Software needs to be parallelized and optimized for accelerators such as GPUs in order to take advantage of the new breed of multi-/many-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.
The tenth edition of the MULTIPROG workshop aims to bring together researchers interested in programming models, runtimes, and computer architecture. The workshop's emphasis is on heterogeneous architectures and covers issues such as:
- How can future parallel programming models improve software productivity?
- How should compilers, runtimes and architectures support programming models and emerging applications?
- How to design efficient data structures and innovative algorithms?
MULTIPROG is intended for quick publication of early results, work-in-progress, etc., and is not intended to prevent later publication of extended papers. Informal proceedings with accepted papers will be made available at the workshop and online at the workshop’s web page http://research.ac.upc.edu/multiprog/.
Papers are sought on topics including, but not limited to:
- Multi-core architectures
- Architectural support for compilers/programming models
- Processor (core) architecture and accelerators, in particular GPUs
- Memory system architecture
- Performance, power, temperature, and reliability issues
- Heterogeneous computing
- Algorithms and data structures for heterogeneous systems
- Applications for heterogeneous computing and real-time graphics
- Programming models for multi-core architectures
- Language extensions
- Run-time systems
- Compiler optimizations and techniques
- Benchmarking of multi-/many-core architectures
- Tools for discovering and understanding parallelism
- Tools for understanding performance and debugging
- Case studies and performance evaluation
|Full paper submission:||Submission deadline: October 21, 2016|
|Notification to authors:||Notification to authors: November 27, 2016|
MULTIPROG accepts contributions of regular research papers and short position papers describing early research on emerging topics. When preparing your submission please adhere to the following format specification:
- Regular research papers: Regular research papers should preferably use LNCS format (up to 12 pages, not including references). Single column (up to 12-Pages) or double column (up to 6-pages) formats are also accepted.
- Short position papers: Short position papers should preferably use LNCS format (4-6 pages, not including references). Single column (4-6 pages) or double column (2-3 pages) formats are alsoaccepted. Papers in this category should explicitly indicate "Position Paper" as part of the title of their manuscript.
- LNCS Latex template: ftp://ftp.springer.de/pub/tex/latex/llncs/latex2e/llncs2e.zip
- Word template: ftp://ftp.springer.de/pub/tex/latex/llncs/word/splnproc1110.zip
Submission link: https://easychair.org/conferences/?conf=multiprog2017
|Miquel Pericàs||Chalmers University of Technology||Sweden||miquelp[at]chalmers.se|
|Vassilis Papaefstathiou||Chalmers University of Technology||Sweden||vaspap[at]chalmers.se|
|Oscar Palomar||Barcelona Supercomputing Center||Spain||oscar.palomar[at]bsc.es|
|Ferad Zyulkyarov||Barcelona Supercomputing Center||Spain||ferad.zyulkyarov[at]bsc.es|
|Abdelhalim Amer||Argonne National Lab||USA|
|Ali Jannesari||TU Darmstadt||Germany|
|Christos Kotselidis||University of Manchester||UK|
|Dong Ping Zhang||AMD||USA|
|Håkan Grahn||Blekinge Institute of Technology||Sweden|
|Hans Vandierendonck||Queen's University of Belfast||UK|
|Kenjiro Taura||University of Tokyo||Japan|
|Oscar Plata||University of Malaga||Spain|
|Pedro Trancoso||University of Cyprus||Cyprus|
|Roberto Gioiosa||Pacific Northwest National Laboratory||USA|
|Sasa Tomic||IBM Research||Switzerland|
|Timothy G. Mattson||Intel Research||USA|
|Trevor E. Carlson||Uppsala University||Sweden|
|Eduard Ayguade||UPC/Barcelona Supercomputing Center||Spain||eduard[at]ac.upc.edu|
|Benedict R. Gaster||University of the West of England||UK||benedict.gaster[at]uwe.ac.uk|
|Per Stenstrom||Chalmers University of Technology||Sweden||pers[at]chalmers.se|
|Osman Unsal||Barcelona Supercomputing Center||Spain||osman.unsal[at]bsc.es|