Tenth International Workshop on

Programmability and Architectures for Heterogeneous Multicores

To be held in conjunction with:
the 12th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC)

Stockholm, Sweden, January 24, 2017


Computer manufacturers have embarked on the many-core roadmap, promising to add more and more cores/hardware threads on their chips. The ever-increasing number of cores and heterogeneity in architectures has placed new burdens on the programming community. Software needs to be parallelized and optimized for accelerators such as GPUs in order to take advantage of the new breed of multi-/many-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.

The tenth edition of the MULTIPROG workshop aims to bring together researchers interested in programming models, runtimes, and computer architecture. The workshop's emphasis is on heterogeneous architectures and covers issues such as:

MULTIPROG is intended for quick publication of early results, work-in-progress, etc., and is not intended to prevent later publication of extended papers. Informal proceedings with accepted papers will be made available at the workshop and online at the workshop’s web page http://research.ac.upc.edu/multiprog/.

Topics of interest

Papers are sought on topics including, but not limited to:


Important dates

Full paper submission: Submission deadline: October 21, 2016
Notification to authors: Notification to authors: November 27, 2016

Paper Submission

MULTIPROG accepts contributions of regular research papers and short position papers describing early research on emerging topics. When preparing your submission please adhere to the following format specification:

The authors of the accepted papers will be requested to provide the final version of their paper in LNCS format. Please use the templates below:

Submission link: https://easychair.org/conferences/?conf=multiprog2017


Miquel Pericàs Chalmers University of Technology Sweden miquelp[at]chalmers.se
Vassilis Papaefstathiou Chalmers University of Technology Sweden vaspap[at]chalmers.se
Oscar Palomar Barcelona Supercomputing Center Spain oscar.palomar[at]bsc.es
Ferad Zyulkyarov Barcelona Supercomputing Center Spain ferad.zyulkyarov[at]bsc.es

Program committee

Abdelhalim Amer Argonne National Lab USA
Ali Jannesari TU Darmstadt Germany
Avi Mendelson Technion Israel
Chris Adeyeni-Jones ARM UK
Christos Kotselidis University of Manchester UK
Dong Ping Zhang AMD USA
Håkan Grahn Blekinge Institute of Technology Sweden
Hans Vandierendonck Queen's University of Belfast UK
Kenjiro Taura University of Tokyo Japan
Magnus Sjalander NTNU Norway
Oscar Plata University of Malaga Spain
Pedro Trancoso University of Cyprus Cyprus
Polyvios Pratikakis FORTH-ICS Greece
Roberto Gioiosa Pacific Northwest National Laboratory USA
Sasa Tomic IBM Research Switzerland
Timothy G. Mattson Intel Research USA
Trevor E. Carlson Uppsala University Sweden
Yungang Bao ICT-CAS China

Steering committee

Eduard Ayguade UPC/Barcelona Supercomputing Center Spain eduard[at]ac.upc.edu
Benedict R. Gaster University of the West of England UK benedict.gaster[at]uwe.ac.uk
Lee Howes Facebook USA lee.howes[at]facebook.com
Per Stenstrom Chalmers University of Technology Swedenpers[at]chalmers.se
Osman Unsal Barcelona Supercomputing Center Spain osman.unsal[at]bsc.es

Webmaster: ferad.zyulkyarov[at]bsc.es