Project Leader
Josep L. Larriba (larri@ac.upc.es) Project Members
Alex Ramirez (aramirez@ac.upc.es) Carlos Navarro: (cnavarro@ac.upc.es) Xavier Serrano: (xserrano@ac.upc.es) Josep Torrellas: (torrella@cs.uiuc.edu) Mateo Valero: (mateo@ac.upc.es)
Project description
The fetch bandwidth of future aggressive processors will be a limiting factor for their performance in the near future. The number of useful instructions per cycle provided to the processor depends on the instruction cache miss rate, the number of instructions provided per access and the branch prediction strategy. In this piece of research, we make use of the Software Trace Cache presented in here (El here hauria de tenir un hiperppunter a la part de compiladors) to evaluate its interaction with the hardware of future aggressive processors. Also, we want to investigate changes to the hardware so that the interaction of both software and hardware improves. First results show that the interaction of our Software Trace Cache (STC) with the classic Hardware Trace Cache (HTC) improves the fetch bandwidth of using only either technique. The results for 16 wide issue processors show that the use of the STC together with the HTC gets a fetch bandwith of 12.1 instructions per cycle compared to the 10.6 of the STC alone or the 8.6 of the HTC. The results are for the PostgreSQL DBMS running the TPC-D workload with 64K byte instruction cache and a 16K byte HTC.