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Project Leader

Josep L. Larriba  (larri@ac.upc.es)

Project Members

Alex Ramirez  (aramirez@ac.upc.es)

Carlos Navarro: (cnavarro@ac.upc.es)

Xavier Serrano: (xserrano@ac.upc.es)

Josep Torrellas: (torrella@cs.uiuc.edu)

Mateo Valero: (mateo@ac.upc.es)

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Project description

The fetch bandwidth of future aggressive processors will be a limiting factorfor their performance in the near future. The number of useful instructions per cycle provided to the processor depends on the instruction cache miss rate, the number of instructions provided per access and the branch prediction strategy. In this piece of research, we propose a compilation technique that improves the fetch bandwidth of wide issue superscalar processors. On one side, the technique improves the instruction cache miss rate by placing sequences of instructions that are used frequently in a logic area of the cache that is free of conflicts. On the other side, we reorganize basic blocks in such a way that those BBs that are executed in sequential order are placed sequentially in memory. With this, two of the three issues relative to fetch bandwidth are being improved. Our results show that our technique improves the fetch bandwidth for the PostgreSQL database running the TPC-D workload on a 64KB instruction cache. The improvement for 16 wide issue processors goes from 5.8 instructions per cycle to 10.6 instructions per cycle for the reorganized code.

This has been simulated with the help of ATOM for code generated by an Alpha workstation. The next step of this project is to generate a post compiler tool to generate code that executes in real processors.