Next: About this document ...
Up: Evaluating Symbolic Traversal Algorithms
Previous: Files
- 1
-
A. Cimatti, E. M. Clarke, F. Giunchiglia, and M. Roveri.
NUSMV: A new symbolic model checker.
International Journal on Software Tools for Technology
Transfer, 2(4):410-425, 2000.
- 2
-
M. R. Greenstreet.
STARI: A technique for high-bandwidth communication.
Technical Report TR-394-92, PhD Thesis, 1993.
- 3
-
M. R. Greenstreet and T. Ono-Tesfaye.
A fast, ASP*, RGD arbiter.
In Proc. International Symposium on Advanced Research in
Asynchronous Circuits and Systems, pages 173-185, 1999.
- 4
-
I. H. Moon, G. D. Hachtel, and F. Somenzi.
Border-block triangular form and conjunction schedule in image
computation.
In Formal Methods in Computer-Aided Design (FMCAD), volume 1954
of Lecture Notes in Computer Science, pages 73-90. Springer-Verlag,
2000.
- 5
-
I. H. Moon, J. H. Kukula, K. Ravi, and F. Somenzi.
To split or to conjoin: the question in image computation.
In Proc. Design Automation Conference, pages 23-28, 2000.
- 6
-
J. Muttersbach, T. Villigers, and W. Fichtner.
Practical design of globally-asynchronous locally-synchronous
systems.
In Proc. International Symposium on Advanced Research in
Asynchronous Circuits and Systems, pages 52-59, 2000.
- 7
-
E. Pastor.
A short introduction to the TranSyT verification tool.
Technical Report RR-2004/14, UPC/DAC, Apr. 2004.
- 8
-
R. K. Brayton, G. D. Hachtel, A. Sangiovanni-Vincentelli, F. Somenzi,
A. Aziz, S.-T. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A.
Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G.
Swamy, and T. Villa.
VIS: a system for verification and synthesis.
In Rajeev Alur and Thomas A. Henzinger, editors, Proceedings
of the Eighth International Conference on Computer Aided Verification CAV,
volume 1102, pages 428-432, New Brunswick, NJ, USA, / 1996. Springer Verlag.
- 9
-
R. Ranjan, A. Aziz, R. Brayton, B. Plessier, and C. Pixley.
Efficient bdd algorithms for fsm synthesis and verification.
In IEEE/ACM International Workshop on Logic Synthesis, Lake
Tahoe, USA, 1995.
- 10
-
K. Ravi and F. Somenzi.
High-density reachability analysis.
In Proc. of the IEEE/ACM International Conference on Computer
Aided Design, pages 154-158, 1995.
- 11
-
K. Ravi and F. Somenzi.
Hints to accelerate symbolic traversal.
In Correct Hardware Design and Verification Methods, Advanced
Research Working Conference, CHARME, volume 1703 of Lecture Notes in
Computer Science, pages 250-264. Springer-Verlag, 1999.
- 12
-
O. Roig, J. Cortadella, and E. Pastor.
Verification of asynchronous circuits by bdd-based model checking of
petri nets.
In International Conference on Application and Theory of Petri
Nets, Lecture Notes in Computer Science, pages 374-391, 1995.
- 13
-
S. Schuster, W. Reohr, P. Cook, D. Heidel, M. Immediato, and K. Jenkins.
Asynchronous Interlocked Pipelined CMOS Circuits
Operating at
GHz.
In IEEE International Solid-State Circuits Conference, pages
292-293, 2000.
- 14
-
M. Solé and E. Pastor.
Traversal techniques for concurrent systems.
In Proc. Formal Methods in Computed-Aided Design (FMCAD 2002),
volume 2517 of Lecture Notes in Computer Science, pages 220-238,
Portland, Oregon, USA, November 2002. Springer-Verlag.
- 15
-
K. Y. Yun and A. E. Dooply.
Pausible clocking based heterogeneous systems.
IEEE Transactions on VLSI Systems, 7(4):482-487, 1999.
Enric Pastor
2004-05-28