Adding a Vector Unit to a Superscalar Processor
Project Leader:
Roger Espasa (roger@ac.upc.es)Project Members
Mateo Valero (mateo@ac.upc.es)Francisca Quintana (paqui@ac.upc.es)
Jesús Corbal (jcorbal@ac.upc.es)
Project Description
The goal of this project is to study the tradeoffs involved in adding a vector unit to a current out-of-order superscalar processor. The vector unit targets three application domains: numerical codes, its traditional realm of application, multimedia codes and bandwidth-hungry commercial applications such as databases. A central aspect of this research involves the design of an adequate on-chip cache hierarchy that can simultaneously handle the needs of traditional scalar/integer code and the bandwidth requirements of the vector unit.
Relevant publications
- "Adding a Vector Unit to a Superscalar Processor"
Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero,
Undisclosed. Submitted to ICS'99. Contact: Francisca Quintana
- See also the "Advanced Vector Architectures" home page