Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Barcelona (Spain), 18-21 April 1999
	SYMPOSIUM PROGRAM

TECHNICAL PROGRAM

KEYNOTE SESSIONS

• The 2000 MHz Bug--End of the Millenium of Synchronous Systems?
  By Richard F. Lyon,
  Foveonics Inc. and California Institute of Technology.
  
  Abstract:
  This year puts us in mind of problems involving the approach of the number 2000, so I thought it would be good to examine the relevance of this number to asynchronous logic. I could have picked a 2000-ps clock period, but since we approach that from above, and since we're basically there already with modern synchronous processors, I thought I better take a look at 2000 MHz. It would be rash to claim that asynchronous techniques might get us there more easily than synchronous, but maybe it would be more realistic to say that synchronous systems at such speeds are just going to be nearly impossible to design, build, and keep working. So maybe there will be a time when logic is so fast, and systems are so slow by comparison, that the asynchronous style will no longer have a speed penalty and the advantages of configurability, stability, low power, etc., will shine through. But that time will only come if we find a way to propagate a design style through the schools and companies that make chips, subsystems, etc. In my recent experience, I find young designers who are very good with synchronous systems, yet who have never heard of our friends Charlie Molnar and synchronizer failure, both of whom are eternal. They build systems with too many crystal oscillators-and somehow make them work (most of the time). Designs such as synchronous pipelined A/D converters that can't work in theory are doing pretty well in practice, with only a few values being corrupted by metastability. There may be an opportunity here if we can educate people just as the problems become severe enough to get their attention. I said about the same thing at the 1994 ASYNC in Salt Lake City, and I'm eager to get caught up on the progress in implementations and education at this millenium-concluding meeting.
  
  
• Exploiting BDDs in Higher Order Logic, with Applications to Asynchronous Circuits.
  By Michael J.C. Gordon,
  Computer Laboratory, University of Cambridge.
  
  Abstract:
  A theorem prover enhanced with BDD-based symbolic state enumeration will be described. An asynchronous arbiter circuit, previously analysed algorithmically (by Lee, Greenstreet, and Seger), will be used as an example.
  
  
• Asynchronous Macromodules were a Pain to Build but a Joy to Use.
  By Wesley A. Clark.
  Clark, Rockoff and Associates.
  
  Abstract:
  Demonstrating the credibility of a 1967 assertion that macromodules would be "building blocks such as registers, adders, memories, control devices, etc., from which it is possible for the electronically-naive to construct arbitrarily large and complex computers that work" [1, 2] required several years of exacting effort, during which many of our current notions in the theory and practice of asynchronous system design -- for example, data bundling and validation, the role of arbitration, "rendezvous" elements, and so on -- met some of their earliest engineering challenges. By the time Washington University's Macromodular Systems Project delivered a final report to its U.S. government sponsors (the National Institutes of Health and the Advanced Research Projects Agency), an inventory of 800 macromodules of 17 distinct types had been established and more than 70 widely different "computers that work" had been constructed, used, and dismantled. How? Why?

  [1] Ornstein, S.M., M.J Stucki, and W.A. Clark, "A functional description of macromodules," AFIPS Proc. Vol 30, 1967, pp 337-355
  [2] Clark, W.A. and C.E. Molnar, "Macromodular Computer Systems," in Computers in Biomedical Research Vol IV, R.W. Stacy and B.D. Waxman, eds, Academic Press, New York, 1974, Chapter 3

DEMO SESSION I (Industry)

• The PCA5007 Pager IC: What Makes it Tick.
  By Kees van Berkel, Philips Research.
  
  
• An HDL methodology for Null Convention Logic.
  By Michiel Ligthart, Theseus Logic.
  
  Abstract:
  "An HDL methodology for Null Convention Logic" describes how Theseus has developed a VHDL based flow with commercial, off-the-shelf tools. After a brief review of NCL it discusses in detail how the VHDL language and tools can support self-timed logic. During his talk, Michiel will actually give a live demo of simulation and synthesis of a small HDL circuit using commercial tools from Mentor Graphics and Veribest.

DEMO SESSION II (Academy)

• Using Balsa for Asynchronous Synthesis
  By Doug Edwards, University of Manchester (UK)
  
  Abstract:
  Balsa is a hardware description language, similar to Tangram, intended for the synthesis of large asynchronous systems. The language features modular compilation, enclosed select sematics, parameterised procedures and recursion. Current backends generate a LARD simulation program and Compass netlists. Work is in progress to embed the system in the Cadence Design Framework. Balsa has been used to generate the DMA controller of the Amulet3H which is a mixed custom/sythesised layout with interfaces to both asynchronous and synchronous subsystems. The demonstration will illustrate design using Balsa.
  
  
• Design of DI Processes
  By Willem Mallon, Groningen University (The Netherlands)
  
  Abstract:
  We present three tools to assist the designer of delay insensitive communicating processes.

  digg

  Transforms recursive DI algebra expressions into XDI automata in the AND/IF format.

  steffi

  Takes an automaton description in AND/IF format and allows for easy interactive drawing on screen.

  ludwig

  Implements composition, decomposition and other operations on XDI automata

  
  
  
• MINIMALIST: an Environment for the Synthesis and Testability of Burst-Mode Asynchronous Machines
  By Steven Nowick, Columbia University (USA)
  
  Abstract:
  MINIMALIST is a new extensible environment for the synthesis, testability and verification of burst-mode asynchronous finite-state machines. It includes a complete technology-independent synthesis path: exact and heuristic algorithms for optimal state assignment, 2-level hazard-free logic minimization, and synthesis-for-testability. It also offers a number of user options (for example to vary code lengths during state assignment), allowing the designer to explore trade-offs. It also supports the addition of new tools via well-defined interfaces.

  Initial benchmark results show an average of 34% and up to 48% less area, and an average of 11% and up to 37% better performance, than other burst-mode packages.
  
  

• CASCADE: a Tool for Deriving Extended-Burst-Mode Machines from STGs.
  By G. Eckstein, University of Kaiserslautern (Germany)
  
  Abstract:
  We can demonstrate the software implementation of the algorithms described in our paper presented in the synthesis session. Via a Motif-GUI, a graphical Petri-Net editor can be invoked which outputs data about the net, from which a set of extended-burst-mode machnines is derived (if possible).
  
  
• di2pn: a Tool for Automated Translation from DI Algebra to Petri Nets
  By Dennis Furey, South Bank University (UK)
  
  Abstract:
  di2pn is a CAD tool that takes delay-insensitive module specifications and translates them into a Petri net suitable for analysis or processing by other tools, such as petrify. The source language is a "sugared" version of DI-Algebra, superficially similar to other specification languages such as Tangram or LARD, but with events designating individual signal transitions rather than complete handshakes. DI-Algebra also benefits from a well defined semantics.