TranSyT Overview

       A Short Introduction to the TranSyT Verification Tool

          E. Pastor, M.A. Peña and M. Sole

          UPC/DAC Technical Report RR-2004/16, April 2004.

Reachability Analysis

       Evaluating Symbolic Traversal Algorithms Applied to Asynchronous Concurrent Systems

          M.Sole and E. Pastor,

          UPC/DAC Technical Report RR-2004/15, April 2004.

       Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems

          E. Pastor and M.A. Peña,

          12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), 

          pages 378-393, L'Aquila, Italy, October 2003.

          Slides used in the conference (Powerpoint format).

       Combining Simulation and Guided Traversal for the Verification of Concurrent Systems

          E. Pastor and M.A. Peña,

          Design, Automation and Test in Europe (DATE), 

          pages 1158-1159, Munich, Germany, March 2003.

          Poster used in the conference (Powerpoint format).

       Traversal Techniques for Concurrent Systems

          M.Sole and E. Pastor,

          4th International Conference on Formal Methods in Computer-Aided Design (FMCAD), 

          pages 220-237, Portland, OR, (USA), November 2002.

          Slides used in the conference (Powerpoint format).

Timed Verification

       A Case Study for the Verification of Complex Timed Circuits: IPCMOS

          M.A. Peña, J. Cortadella, E. Pastor and A. Smirnov,

          Design, Automation and Test in Europe (DATE), 

          pages 44-51, Paris, France, March 2002.

          Slides used in the conference (Powerpoint format).

       Formal Verification of Safety Properties in Timed Circuits
          M.A. Peña, J. Cortadella, A. Kondratyev and E. Pastor,
          International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), 

          pages 2-11, Eilat, Israel, April 2000.
          Slides used in the conference (Powerpoint format).