Computer architecture is at the interface of what the software requires and what the hardware carries out. From one side, there are untapped opportunities for computers to solve problems. From the other side, the process technology people are promising 10 billion transistors on a die, operating at 10 GHz. That many transistors means even a single boring chip can have 200 Pentium 4 processors on it. We are in the middle -- what should we do. Some gurus have told us to do nothing, that all that can be done has been done. Others tell us we as a community need some shaking up. I think both are wrong, and that there is much we can do. I think there are areas that traditionally we have not thought of as within our sphere of influence where we could have important impact -- that is, each provides an opportunity, if we are willing to take on the accompanying responsibility. Algorithms, programming, education immediately come to mind. I might also talk about what I think future chcips might look like, if we have time.
Abstract-- New computer architectures are being proposed and will be implanted in the next few years. A common trend to improve the system performance is to include some reconfigurable logic components into future multi-core chips. Several prototypes already exist but there still is a lack of support from the programming models, the compilers and the operating system. Reconfigurable architectures enable a new execution model based on hardware accelerators. There have been several efforts in the last few years to extend the thread abstraction to include the characteristics of these new reconfigurable elements. However, since the thread abstraction was conceived to abstract the CPU, the inherent model is different from what hardware accelerators should expect. In this paper we present a new way of managing hardware accelerators. We propose a new programming and execution model for hardware accelerators based on the processing unit abstraction. We study the relationship between hardware accelerators and the processor architecture, exploring the features that the new reconfigurable architectures should provide to the operating system. We also show how a prototype hardware accelerator achieves a 1.78x speed-up over the software implementation of the same functionality, out of a 41x potential speed-up, due to the data communication overhead. Finally we show our work on dynamic partial reconfiguration and how it enables using the processing unit abstraction to provide virtual reconfigurable logic.
Since the approach of building specialized systems from existing general-purpose components is becoming more common, there is a growing need for global optimization tools that accomplish the functional requirements of these systems. The first approach for developers is to apply the current optimization techniques individually on each component. Nevertheless, these optimizations do not always improve the code enough and manual tuning must be done afterward. This paper presents a new approach for global optimization based on building a global view of the system, a global control flowgraph. The paper summarizes relevant characteristics of the system components to build a global view and presents particular examples for different architectures (PowerPC and x86) and operating systems (based on L4 kernel and Linux kernel). Our evaluations show that typical optimizations on a specific embedded environment reduce the code size by up to 54%.
Web-Services, SOAP and Service-oriented Architectures are gaining momentum in the area of distributed systems and internet applications. However, as we increase the abstraction level of the applications we are also increasing the complexity of the underlying middleware. In this talk, i will present a dependability benchmarking study to evaluate and compare the robustness of some of the most popular SOAP-RPC implementations that are intensively used in the industry. This benchmarking framework has support for different packages of middleware for client-server applications, like TCP/IP sockets, Java RMI, HTTP-XML and SOAP. The study was focused in detail on Apache Axis. The results of this benchmarking study should be seen as a contribution for the study of the impact of the complexity of the SOAP middleware in the dependability of SOA applications. In particular, we have observed a high susceptibility of software aging in this particular implementation of SOAP (Apache Axis1.3). Building on these results we propose a new SLA-oriented software rejuvenation technique that proved to be a simple way to increase the dependability of the SOAP-servers, the degree of self-healing and to maintain a sustained level of performance in the applications. Keywords : Dependability benchmarking; Dependable Web-Services; Self-healing systems; Software rejuvenation; Software aging; Autonomic Computing
Conventionally, programmers use standard -Ox settings which are provided by compiler developers. However, in order to obtain maximal performance, it is necessary to tune the compiler setting for the application as well as the underlying architecture. We propose a methodology to configure compiler options automatically using profile information. We apply statistical analysis to decide whether to turn on or to turn off compiler flags. This approach produces compiler settings of gcc3.3.1 for the SPEC2000 benchmark suite that outperform the O3 setting on three representative architectures: Pentium4, SPARC, and IA64.
The availability of software and hardware systems can be increased by preventive measures which are triggered by failure prediction mechanisms. We present and evaluate two techniques which model and predict the occurrence of failures as a function of discrete and continuous measurements of system variables. We employ two modelling approaches: an extended Markov chain model and a function approximation technique utilising universal basis functions (UBF). The presented modelling methods are data driven rather than analytical and can handle large amounts of variables and data. They offer the potential to capture the underlying dynamics of high-dimensional and noisy systems. Both modelling techniques have been applied to real data of a commercial telecommunication platform. The data includes event-based log files and measured system states. Results are presented in terms of precision, recall, F-Measure and cumulative cost. We compare our results to standard techniques such as linear ARMA models. Our findings suggest significantly improved forecasting performance compared to alternative approaches. By using the presented modelling techniques the system availability may be improved by an order of magnitude. We conjecture that the UBF approach can be used successfully for performance prediction in both single and multiprocessor systems.
Per diferents raons economiques i tambe ecologiques, minimitzar el consum energetic dels dispositius de computacio s'esta convertint en un avantatge competitiu a la industria, molt especialment a l'hora de vendre a grans comptes com governs i corporacions. El dispositiu ideal seria aquell que adaptes el seu consum energetic a la feina util que estigui realitzant en cada moment, tot evitant malbaratar energia. El Sistema Operatiu es troba en el millor punt per avaluar en cada moment les necessitats energetiques i per coordinar els canvis d'estat necessaris per a modificar dinamicament els perfils de consum, i l'electronica cada vegada ofereix mes punts de control per poder modular el consum. A la industria hi ha algunes aproximacions mes aviat barroeres, en parlarem i veurem les oportunitats per fer aportacions interessants en aquesta area
One of the projects of SSD (Supercomputer Software Department) is presented. Assembly technology oriented to the development of high performance parallel programs of numerical modeling is discussed. The technology provides automatically such dynamic properties of application programs as dynamic tuning to the available resources, dynamic load balancing, etc. The technology application is demonstrated by the parallel implementation of the large scale model based on Particle-In-Cell (PIC) method. 1. About SSD and Chairs 2. Short review of the basic project of SSD 3. Methods of the PIC parallelization 4. Parallel PIC implementation 5. Modeling of Galaxy and Protoplanetary disc evolution
That's all folks!!!!!