Universitat Politčcnica de Catalunya
High Performance Computing Group
Departament d'Arquitectura de Computadors,
Universitat Politčcnica de Catalunya
Departament d'Arquitectura de Computadors
 
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2000 HPC Group Publications

PhD Thesis

  • Enric Fontdecaba. High Performance Algorithms for Progressive Addition Lens Design. PhD thesis, Universitat Politčcnica de Catalunya (UPC), July 2000. Advisor José M. Cela.

  • José González. Speculative Execution Through Value Prediction. PhD thesis, Universitat Politčcnica de Catalunya (UPC), January 2000. Advisor Antonio González.

Journals

  • Alex Ramírez, Josep-L. Larriba-Pey and Mateo Valero. A Stream Processor Front-end. IEEE Technical Committee on Computer Architecture Newsletter, pp. 10-13, June 2000.

  • Ernest Artiaga, Albert Serra and Marisa Gil. Porting Multithreading Libraries to an Exokernel System. ACM Operating Systems Review, pp. 121-126, vol. SI, September 2000. ACM SIGOPS European Workshop 2000.

  • Jesús Sánchez and Antonio González. Analyzing Data Locality in Numeric Applications. IEEE Micro, pp. 58-66, vol. 20, no. 4, July 2000.

  • Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta, José I. Navarro and José Oliver. NanosCompiler: Supporting Flexible Multilevel Parallelism Exploitation in OpenMP. Concurrency, pp. 1205-1218, vol. 12, no. 12, October 2000.

  • Nerina Bermudo, Xavier Vera, Antonio González and Josep Llosa. Optimizing Cache Miss Equation Polyhedra. ACM, Computer Architecture News, pp. 43-52, vol. 28, no. 1, March 2000.

  • Sergi Girona and Jesús Labarta. Sensitivity of Performance Prediction of Message Passing Programs. Journal of Supercomputing, pp. 291-298, vol. 17, no. 3, November 2000.

  • Toni Cortés, Yolanda Becerra and Raul Cervera. Swap compression: ressurecting old ideas. Software-Practice & Experience, pp. 567-587, vol. 30, no. 5, May 2000.

Conference Proceedings

  • Albert Serra, José I. Navarro and Toni Cortés. DITools: Application-level Support for Dynamic Extension and Flexible Composition . In USENIX Annual Technical Conference (USENIX'2000), pp. 225-238, June 2000.

  • Alex Ramírez, Josep-L. Larriba-Pey and Mateo Valero. Trace Cache Redundancy: Red & Blue Traces. In Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000), pp. 325-333, January 2000.

  • Alex Ramírez, Josep-L. Larriba-Pey and Mateo Valero. The Effect of Code Reordering on Branch Prediction. In International Conference on Parallel Architectures and Compilation Techniques 2000 (PACT 2000), pp. 189-198, October 2000.

  • Alex Ramírez, Josep-L. Larriba-Pey and Mateo Valero. Semi-static branch prediction for optimized code layouts. In 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3), pp. - , January 2000.

  • Markus Ast, Cristina Barrado, José M. Cela, R. Fisher, Jesús Labarta, O. Laborda, H. Manz and U. Schulz. Sparse Matrix Structure for Dynamic Parallelisation Efficiency. In 6th International Euro-Par Conference (EuroPar'2000), pp. 519-526, August 2000.

  • Carlos Navarro, Alex Ramírez, Josep-L. Larriba-Pey and Mateo Valero. On the Performance of Fetch Engines Running DSS Workloads. In 6th International Euro-Par Conference (EuroPar'2000), pp. 591-595, August 2000.

  • Carlos Navarro, Alex Ramírez, Josep-L. Larriba-Pey and Mateo Valero. Fetch negines and databases. In 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3), pp. - , January 2000.

  • José Lorenzo Cruz, Antonio González, Mateo Valero and Nigel P. Topham. Multiple-Banked Register File Architectures. In 27th Annual International Symposium on Computer Architecture (ISCA'2000), pp. 316-325, June 2000.

  • Dolors Royo, Nirav Kapadia and José A.B. Fortes. Running PVM Applications in the PUNCH Wide Area Network-Computing Environment. In 4th International meeting VECPAR-2000, pp. 90-95, June 2000.

  • Enric Morancho, José M. Llabería and Angel Olivé. Two-Level Address Storage and Address Prediction. In 6th International Euro-Par Conference (EuroPar'2000), pp. 960-964, August 2000.

  • Jesús Sánchez and Antonio González. The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. In 29th. Int. Conf. on Parallel Processing (ICPP-2000), pp. 555-562, August 2000.

  • Jesús Sánchez and Antonio González. Instruction Scheduling for VLIW Architectures. In 13th International Symposium on System Synthesis (ISSS-2000), pp. 41-46, September 2000.

  • Jesús Sánchez and Antonio González. Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture. In 33th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pp. 124-133, December 2000.

  • Jesús Labarta, Eduard Ayguadé, José Oliver and David Henty. New OpenMP Directives for Irregular Data Access Loops. In 2nd European Workshop on OpenMP (EWOMP2000), pp. 91-97, September 2000.

  • Jordi Guitart, Jordi Torres, Eduard Ayguadé, José Oliver and Jesús Labarta. Java Instrumentation Suite: Accurate Analysis of Java Threaded Applications. In 2nd Annual Workshop on Java for High-Performance Computing, pp. 15-25, May 2000.

  • Jordi Guitart, Jordi Torres, Eduard Ayguadé, José Oliver and Jesús Labarta. Instrumentation Environment for Java Threaded Applications. In XI Jornadas de Paralelismo, pp. 89-94, September 2000.

  • Joan M. Parcerisa and Antonio González. Reducing Wire Delay Penalty through Value Prediction. In 33th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pp. 317-326, December 2000.

  • José Oliver, Eduard Ayguadé and José I. Navarro. Towards an Efficient Exploitation of Loop-level Parallelism in Java. In ACM Java Grande 2000 Conference, pp. 9-15, June 2000.

  • Julita Corbalán, Xavier Martorell and Jesús Labarta. Performance-Driven Processor Allocation. In Symposium on Operating Systems Design and Implementation (OSDI 2000), pp. 59-71, October 2000.

  • Javier Zalamea, Josep Llosa, Eduard Ayguadé and Mateo Valero. Improved Spill Code Generation for Software Pipelined Loops. In ACM SIGPLAN'00 Conference on Programming Language Design and Implementation (PLDI'2000), pp. 134-144, June 2000.

  • Javier Zalamea, Josep Llosa, Eduard Ayguadé and Mateo Valero. Two-level Hierarchical Register File Organization for VLIW Processors. In 33th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pp. 137-146, December 2000.

  • Luis Díaz de Cerio, Miguel Valero-García and Antonio González. Complete Exchange Algorithms for Meshes and Tori Using a Systematic Approach. In 6th International Euro-Par Conference (EuroPar'2000), pp. 591-594, August 2000.

  • Marc González, Albert Serra, Xavier Martorell, José Oliver, Eduard Ayguadé, Jesús Labarta and José I. Navarro. Applying Interposition Techniques for Performance Analysis of OpenMP Parallel Applications. In 14th International Parallel and Distributed Processing Symposium (IPDPS'2000), pp. 235-240, May 2000.

  • Marc González, José Oliver, Xavier Martorell, Eduard Ayguadé, Jesús Labarta and José I. Navarro. OpenMP Extensions for Thread Groups and Their Runtime Support. In 13th International Workshop on Programming Languages and Compilers for Parallel Computing (LCPC'00), pp. 324-338, December 2000. Lecture Notes in Computer Science vol. 2017.

  • Marc González, Xavier Martorell, José Oliver, Eduard Ayguadé and Jesús Labarta. Code Generation and Run-time Support for Multi-level Parallelism Exploitation. In International Workshop on Compilers for Parallel Computers, pp. 291-301, January 2000.

  • Marc González, José Oliver, Xavier Martorell, Eduard Ayguadé, Jesús Labarta and José I. Navarro. Precedence Relations in the OpenMP Programming Model. In 2nd European Workshop on OpenMP (EWOMP2000), pp. 58-67, September 2000.

  • Marta Jiménez, José M. Llabería and Agustín Fernández. On the Performance of Hand vs Automatically Optimized Numerical Codes. In Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000), pp. 183-194, January 2000.

  • Dimitrios Nikolopoulos, Theodore Papatheodorou, C.D. Polychronopoulos, Jesús Labarta and Eduard Ayguadé. A Case for User-Level Dynamic Page Migration. In International Conference on Supercompting (ICS'2000), pp. 119-130, May 2000.

  • Dimitrios Nikolopoulos, Theodore Papatheodorou, C.D. Polychronopoulos, Jesús Labarta and Eduard Ayguadé. UPMLIB: A Runtime System for Tuning the Memory Performance of OpenMP Programs on Scalable Shared-memory Multiprocessors. In 5th ACM Workshop on Languages, Compilers and Run-time Systems for Scalable Computers (LCR2000), pp. 85-99, May 2000. Lecture Notes in Computer Science vol. 1915.

  • Dimitrios Nikolopoulos, Theodore Papatheodorou, C.D. Polychronopoulos, Jesús Labarta and Eduard Ayguadé. User-level Dynamic Page Migration for Multiprogrammed Shared-memory Multiprocessors. In 29th. Int. Conf. on Parallel Processing (ICPP-2000), pp. 95-103, August 2000.

  • Dimitrios Nikolopoulos, Theodore Papatheodorou, C.D. Polychronopoulos, Jesús Labarta and Eduard Ayguadé. Leveraging Transparent Data Distribution in OpenMP via User-level Dynamic Page Migration. In 3rd International Symposium on High-performance Computing (ISHPC2000), pp. 415-425, October 2000. Lecture Notes in Computer Science vol. 1940.

  • Dimitrios Nikolopoulos, Theodore Papatheodorou, C.D. Polychronopoulos, Jesús Labarta and Eduard Ayguadé. Is Data Distribution Necessary in OpenMP?. In IEEE/ACM Supercomputing'2000, pp. 10-20, November 2000.

  • Pedro Marcuello and Antonio González. A Quantitative Assesment of Thread-Level Speculation Techniques. In 14th International Parallel and Distributed Processing Symposium (IPDPS'2000), pp. 595-601, May 2000.

  • Ramon Canal, Joan M. Parcerisa and Antonio González. Dynamic Cluster Assignament Mechanisms. In Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000), pp. 133-142, January 2000.

  • Ramon Canal and Antonio González. A Low-Complexity Issue Logic. In International Conference on Supercompting (ICS'2000), pp. 327-335, May 2000.

  • Ramon Canal, Antonio González and James E. Smith. Very Low Power Pipelines using Significance Compression . In 33th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pp. 181-190, December 2000.

  • Ronaldo Gonçalves, Eduard Ayguadé, Mateo Valero and Philippe Navaux. A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies. In 12th Symposium on Computer Architecture and High Performance Computing, pp. 279-286, October 2000.

  • Sergi Girona, Jesús Labarta and Rosa M. Badia. Validation of Dimemas communication model for MPI collective operations. In 7th EuroPVM/MPI'2000, pp. 27-38, September 2000.

  • Toni Cortés and Jesús Labarta. A Case for Heterogenenous Disk Arrays. In IEEE International Conference on Cluster Computing , pp. 319-325, November 2000.

  • Xavier Martorell, Julita Corbalán, Dimitrios Nikolopoulos, José I. Navarro, Eleftherios Polychronopoulos, Theodore Papatheodorou and Jesús Labarta. A Tool to Schedule Parallel Applications on Multiprocessors: the NANOS CPU Manager. In 6th Annual Workshop on Job Scheduling Strategies for Parallel Processing, pp. 55-69, May 2000.

  • Xavier Vera, Nerina Bermudo, Antonio González and Josep Llosa. An Efficient Solver for Cache Miss Equations. In 2000 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 139-145, April 2000.

  • Xavier Vera, Josep Llosa, Antonio González and Nerina Bermudo. A Fast and Accurate Approach to Analyze Cache Memory Behavior. In 6th International Euro-Par Conference (EuroPar'2000), pp. 194-198, August 2000.

  • Xavier Vera, Josep Llosa, Antonio González and Carlos Ciuraneta. A Fast Implementation of Cache Miss Equations. In International Workshop on Compilers for Parallel Computers, pp. 319-326, January 2000.



Last Updated: Oct 2004 by HPC-WebMaster