1999 HPC Group Publications

PhD Thesis

• Dolors Royo. Una Contribució al Càlcul de Valors i Vectors Propis i a l'Anàlisi de l'Escalabilitat. PhD thesis, Universitat Politècnica de Catalunya (UPC), January 1999. Advisor Miguel Valero-García.

• Luis A. Villa. Evaluación de Arquitecturas Vectoriales Avanzadas en Registros Cortos. PhD thesis, Universitat Politècnica de Catalunya (UPC), July 1999. Advisor Mateo Valero and Roger Espasa.

• Marta Jiménez. Multilevel Tiling for Non-Rectangular Iteration Spaces. PhD thesis, Universitat Politècnica de Catalunya (UPC), May 1999. Advisor Agustín Fernández. Available as Technical Report UPC-DAC-1999-16.

• Xavier Martorell. Dynamic Scheduling of Parallel Applications on Shared-Memory Multiprocessors. PhD thesis, Universitat Politècnica de Catalunya (UPC), July 1999. Advisor Jesús Labarta and José I. Navarro.

Journals

• Dolors Royo, Antonio González and Miguel Valero-García. Low Communication Overhead Jacobi Algorithms for Eigenvalue Computation on Hypercubes. Journal of Supercomputing, pp. 171-194, vol. 14, no. 2, January 1999.

• Jesús Sánchez and Antonio González. Software Data Prefetching for Software Pipelined Loops. Journal of Parallel and Distributed Computing, pp. 236-259, vol. 58, no. 2, August 1999.

• Mateo Valero. Computadors per al proper mil.leni. TERAFLOP, pp. 6-8, no. 45, October 1999.

• Mateo Valero and Veljko Milutinovic. The Evolution of Cache Memories. IEEE Transactions on Computers, pp. 97-99, February 1999.

• Miguel Valero-García. A Proposal of Computer Architecture Courses for the Computer Engineering Curricula of the Polytechnic University of Catalunya. IEEE Technical Committee on Computer Architecture Newsletter, pp. 69-71, February 1999.

• Roger Espasa and Mateo Valero. A Simulation Study of Decoupled Vector Architectures. Journal of Supercomputing, pp. 129-152, vol. 14, no. 2, October 1999.

• Nigel Topham and Antonio González. Randomized Cache Placement for Eliminating Conflicts. IEEE Transactions on Computers, vol. 48, no. 2, February 1999.

Conference Proceedings

• Albert Serra, Xavier Martorell, Ernest Artiaga, Yolanda Becerra, Marisa Gil and José I. Navarro. Herramientas para la Extensibilidad en Entornos de Ejecución Paralelos. In X Jornadas de Paralelismo, pp. 201-206, September 1999.

• Antonio González, Jordi Tubella and Carlos Molina. Trace-Level Reuse. In International Conference on Parallel Processing (ICPP'1999), pp. 30-37, September 1999.

• Alex Ramírez, Josep-L. Larriba-Pey, Carlos Navarro, Xavier Serrano, Josep Torrellas and Mateo Valero. Optimization of Instruction Fetch for Decision Support Workloads. In International Conference on Parallel Processing (ICPP'1999), pp. 238-245, September 1999.

• Alex Ramírez, Josep-L. Larriba-Pey, Carlos Navarro, Josep Torrellas and Mateo Valero. Software Trace Cache. In International Conference on Supercomputing (ICS'1999), pp. 119-126, June 1999.

• Alex Ramírez, Josep-L. Larriba-Pey and Mateo Valero. Trace Cache Redundancy. In X Jornadas de Paralelismo, pp. 39-44, September 1999.

• Alex Ramírez, Josep-L. Larriba-Pey, Carlos Navarro, Xavier Serrano, Josep Torrellas and Mateo Valero. Optimizing instruction fetch for decision support workloads. In 2nd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-2), pp. - , January 1999.

• Carlos Molina, Antonio González and Jordi Tubella. Dynamic Removal of Redundant Computations. In International Conference on Supercomputing (ICS'1999), pp. 474-481, June 1999.

• Carlos Molina, Antonio González and Jordi Tubella. Reducing Memory Traffic Via Redundant Store Instructions. In 7th International Conference High-Performance Computing and Networking, HPCN Europe 1999, pp. 1246-1249, April 1999.

• José Lorenzo Cruz, Antonio González, Mateo Valero and Nigel Topham. A Register File Cache. In X Jornadas de Paralelismo, pp. 9-14, September 1999.

• David López, Josep Llosa, Eduard Ayguadé and Mateo Valero. Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. In International Conference on Parallel Processing (ICPP'1999), pp. 22-29, September 1999.

• Daniel Jiménez, Josep-L. Larriba-Pey and Juan J. Navarro. Communication Conscious Radix Sort. In International Conference on Supercomputing (ICS'1999), pp. 76-82, June 1999.

• Daniel Jiménez, Enric Guinovart, Josep-L. Larriba-Pey and Juan J. Navarro. Sorting on the SGI O2000: Comparing MPI and Shared Memory Implementations. In International Conference of the Chilean Computer Science Society (SCCC'99), pp. 209-215, November 1999.

• Dolors Royo, Miguel Valero-García and Antonio González. Jacobi Ordering for Multiple-port Hypercubes. In Workshop on Frontiers of Parallel Numerical Computations and Applications (Frontiers'99), pp. 1-10, February 1999.

• Daniel Ortega, Iván Martel, Venkata Krishnan, Eduard Ayguadé and Mateo Valero. Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multithreading Architectures. In The 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT'99), pp. 117-124, October 1999.

• Daniel Ortega, Iván Martel, Venkata Krishnan, Eduard Ayguadé and Mateo Valero. A Characterisation of Parallel SPECint Programs in Simultaneous Multi-Threading Architectures. In X Jornadas de Paralelismo, pp. 119-124, September 1999.

• Eleftherios D. Polychronopoulos, Dimitrios Nikolopoulos, Theodore Papatheodorou, Xavier Martorell, Jesús Labarta and José I. Navarro. An Efficient Kernel-Level Scheduling Methodology for Multiprogrammed Shared Memory Multiprocessors. In 12th International Conference on Parallel and Distributed Computing Systems (PDCS'99), pp. 148-155, August 1999.

• Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Marc González and José I. Navarro. Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study. In International Conference on Parallel Processing (ICPP'1999), pp. 172-180, September 1999.

• Eduard Ayguadé, Marc González, Jesús Labarta, Xavier Martorell, José I. Navarro and José Oliver. NanosCompiler: A Research Platform for OpenMP Extensions. In 1st European Workshop on OpenMP (EWOMP'99), pp. 27-31, September 1999.

• Enric Morancho, José M. Llabería and Angel Olivé. Looking at History to Filter Allocations in Predictions Tables. In The 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT'99), pp. 314-319, October 1999.

• Enric Morancho, José M. Llabería and Angel Olivé. Two-Level Address Storage and Address Prediction. In X Jornadas de Paralelismo, pp. 29-37, September 1999.

• Esther Salamí, Jesús Corbal, Roger Espasa and Mateo Valero. An Evaluation of Different DLP Alternatives for the Embedded Media Domain. In 1st Workshop on Media Processors and DSPs (MPDSP-1), pp. 100-109, November 1999.

• Jesús Sánchez and Antonio González. A Locality Sensitive Multi-Module Cache with Explicit Management. In International Conference on Supercomputing (ICS'1999), pp. 51-59, June 1999.

• Jesús Sánchez and Antonio González. Caching Data According to their Locality. In 12th Int. Conf. on Control Systems and Computer Science (CSCS-12), pp. 139-144, May 1999.

• Iván Martel, Daniel Ortega, Eduard Ayguadé and Mateo Valero. Increasing Effective IPC by Exploiting Distant Parallelism. In International Conference on Supercomputing (ICS'1999), pp. 348-355, June 1999.

• Jesús Corbal, Mateo Valero and Roger Espasa. Exploiting a New Level of DLP in Multimedia Applications. In 32nd Annual ACM/IEEE International Symposium on MicroArchitecture (MICRO-32), pp. 72-79, November 1999.

• Jesús Corbal, Roger Espasa and Mateo Valero. MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. In Supercomputing 99 (SC'99), pp. 1-12, November 1999. Published in CD-ROM.

• Joan M. Parcerisa and Antonio González. The Synergy of Multithreading and Access/Execute Decoupling. In The Fifth International Symposium on High-Performance Computer Architecture (HPCA'1999), pp. 59-63, January 1999.

• José González and Antonio González. Control-flow Speculation through Value Prediction for Superscalar Processors. In The 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT'99), pp. 57-65, October 1999.

• Javier Zalamea, Josep Llosa, Eduard Ayguadé and Mateo Valero. Memory Controlled Spill Code for Software Pipelining. In X Jornadas de Paralelismo, pp. 131-136, September 1999.

• M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam and Eduard Ayguadé. An Integer Linear Programming Approach for Optimizing Cache Locality. In International Conference on Supercomputing (ICS'1999), pp. 500-509, June 1999.

• Marcio M. Fernandes, Josep Llosa and Nigel Topham. Distributed Modulo Scheduling. In The Fifth International Symposium on High-Performance Computer Architecture (HPCA'1999), pp. 130-134, January 1999.

• Marcio M. Fernandes, Josep Llosa and Nigel P. Topham. A Scalable VLIW Core for Media Processors. In 1st Workshop on Media Processors and DSPs (MPDSP-1), pp. - , November 1999.

• Manel Fernández and Roger Espasa. Dixie: A Retargetable Binary Instrumentation Tool. In X Jornadas de Paralelismo, pp. 143-148, September 1999.

• Manel Fernández and Roger Espasa. Dixie: A Retargetable Binary Instrumentation Tool. In 1st Workshop on Binary Translation, pp. 1-9, October 1999.

• Francisca Quintana, Jesús Corbal, Roger Espasa and Mateo Valero. Adding a Vector Unit to a Superscalar Processor. In International Conference on Supercomputing (ICS'1999), pp. 1-10, June 1999.

• XXXXXXXXXX and Mateo Valero. Instruction Level Parallelism and Uniprocessor Architecture. In 5th International Euro-Par Conference (Euro-Par'99), pp. 1241-1242, January 1999.

• Patricia Borensztejn, Cristina Barrado and Jesús Labarta. Influence of Variable Time Operations in Static Instruction Scheduling. In 5th International Euro-Par Conference (Euro-Par'99), pp. 213-216, January 1999.

• Pedro Marcuello, Jordi Tubella and Antonio González. Value Prediction for Speculative Multithreaded Architectures. In 32nd Annual ACM/IEEE International Symposium on MicroArchitecture (MICRO-32), pp. 230-236, November 1999.

• Pedro Marcuello and Antonio González. Clustered Speculative Multithreaded Processors. In International Conference on Supercomputing (ICS'1999), pp. 365-372, June 1999.

• Pedro Marcuello, Jordi Tubella and Antonio González. The Increment Predictor for Speculative Multithreaded Processors. In X Jornadas de Paralelismo, pp. 113-118, September 1999.

• Pedro Marcuello and Antonio González. Exploiting Speculative Thread-Level Parallelism on a SMT Processor. In 7th International Conference High-Performance Computing and Networking, HPCN Europe 1999, pp. 754-763, April 1999.

• Q. Cao, Pedro Trancoso, Josep-L. Larriba-Pey, Josep Torrellas, R. Knighten and Y. Won. Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. In 1999 IEEE International Conference on Computer Design (ICCD'99), pp. 108-115, October 1999.

• Ramon Canal, Joan M. Parcerisa and Antonio González. A Cost-Effective Clustered Architecture. In The 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT'99), pp. 160-168, October 1999.

• Raul Cervera, Toni Cortés and Yolanda Becerra. Improving Application Performance through Swap Compression. In 1999 USENIX Annual Technical Conference, pp. 207-218, June 1999.

• Sergi Girona and Jesús Labarta. Sensitivity of Performance Prediction of Message Passing Programs. In International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'99), pp. 620-626, June 1999.

• Sergi Girona, Santi Bello, Jesús Labarta, Pablo Ribes, Román Martín, José Soto and Gloria Laffitte. The Queue System within PHASE. In 7th International Conference High-Performance Computing and Networking, HPCN Europe 1999, pp. 1171-1174, April 1999.

• Teresa Monreal, Antonio González, Mateo Valero, José González and Victor Viñals. Delaying Physical Register Allocation Through Virtual-Physical Registers. In 32nd Annual ACM/IEEE International Symposium on MicroArchitecture (MICRO-32), pp. 186-192, November 1999.

• Toni Cortés and Jesús Labarta. HRaid: a Flexible Storage-System Simulator. In International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'99), pp. 772-778, June 1999.

• Toni Cortés and Jesús Labarta. Linear Aggresive Prefetching: A Way to Increase the Performance of Cooperative Caches. In 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing (IPPS/SPDP'1999), pp. 46-54, April 1999.

• Xavier Martorell, Eduard Ayguadé, José I. Navarro, Julita Corbalán, Marc González and Jesús Labarta. Thread Fork/Join Techniques for Multi-level Parallelism Exploitation in NUMA Multiprocessors. In International Conference on Supercomputing (ICS'1999), pp. 294-301, June 1999.

• Xavier Martorell, Eduard Ayguadé, Jesús Labarta and José I. Navarro. Improving the Performance of Multiprogrammed Workloads in Origin2000 Systems. In 5th European Cray/SGI MPP Workshop, pp. 70-80, September 1999.

Book Chapters

• Dolors Royo, Miguel Valero-García and Antonio González. Jacobi Orderings for Multiple-port Hypercubes. In Parallel Numerical Computation with Applications, Kluwer Academic Publishers, September 1999.

• Eduard Ayguadé. Multiple entries in the area of Computer Engineering. In Comprehensive Dictinonary of Electrical Engineering, CRC Press / IEEE Press, May 1999.

• Toni Cortés. Software RAID and Parallel Filesystems. In High Performance Cluster Computing: Architectures and Systems, Prentice Hall, May 1999.