1998 HPC Group Publications

PhD Thesis

• Toni Juan. Technology-Conscious Cache Design. PhD thesis, Universitat Politècnica de Catalunya (UPC), May 1998. Advisor Juan J. Navarro.

• David López. Recursos anchos: una técnica de bajo coste para explotar paralelismo agresivo en códigos numéricos. PhD thesis, Universitat Politècnica de Catalunya (UPC), December 1998. Advisor Mateo Valero and Josep Llosa.

• Luis Díaz de Cerio. CALMANT: Un Metodo Sistemático para la Ejecución de Algoritmos con Topología Hipercubo en Multicomputadores. PhD thesis, Universitat Politècnica de Catalunya (UPC), December 1998. Advisor Miguel Valero-García and Antonio González. Available as Technical Report UPC-DAC-2000-13.

• Patricia Borensztejn. Medidas de Paralelismo: Un Estudio sobre sus Límites en los Programas Reales. PhD thesis, Universitat Politècnica de Catalunya (UPC), December 1998. Advisor Jesús Labarta.

Journals

• Eduard Ayguadé, Jordi Garcia and Uli Kremer. Tools and Techniques for Automatic Data Layout: A Case Study. Parallel Computing, pp. 557-578, vol. 24, no. 4, May 1998. Special Issue on Languages and Compilers for Parallel Computers.

• Josep Llosa, Mateo Valero, Eduard Ayguadé and Antonio González. Modulo Scheduling With Reduced Register Pressure. IEEE Transactions on Computers, pp. 625-638, vol. 47, no. 6, June 1998.

• Josep Llosa, Eduard Ayguadé and Mateo Valero. Quantitative Evaluation of Register Pressure on Software Pipelined Loops. International Journal of Parallel Programming, pp. 121-142, vol. 26, no. 2, April 1998.

• Luis Díaz de Cerio, Antonio González and Miguel Valero-García. A Method for Exploiting Communication/Computation Overlap in Hypercubes. Parallel Computing, pp. 221-245, vol. 24, no. 2, June 1998.

Conference Proceedings

• Anna M. del Corral and José M. Llabería. New Access Order to Reduce Inter-Vector-Conflicts. In The 3rd International Meeting on Vector and Parallel Processing (VECPAR'98), pp. 367-380, June 1998.

• Antonio González, José González and Mateo Valero. Virtual-Physical Registers. In The Fourth International Symposium on High-Performance Computer Architecture (HPCA'98), pp. 175-184, January 1998.

• Toni Juan, Sanji Sanjeevan and Juan J. Navarro. Dynamic History-Length Fitting: A third level of adaptivity for branch prediction. In The 25th Annual International Symposium on Computer Architecture (ISCA'98), pp. 155-166, July 1998.

• David López, Josep Llosa, Mateo Valero and Eduard Ayguadé. Resource Widening versus Replication: Limits and Performance-Cost Trade-off. In International Conference on Supercomputing (ICS'1998), pp. 441-448, July 1998.

• David López, Josep Llosa, Mateo Valero and Eduard Ayguadé. Widening Resources: A Cost-Efective Technique for Aggressive ILP Architectures. In IX Jornadas de Paralelismo, pp. 243-250, September 1998.

• David López, Josep Llosa, Mateo Valero and Eduard Ayguadé. Widening Resources: A Cost-Efective Technique for Aggressive ILP Architectures. In 31st Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-31), pp. 237-246, November 1998.

• Dolors Royo, Antonio González and Miguel Valero-García. Jacobi Orderings for Multi-Port Hypercubes. In 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP'1998), pp. 88-97, March 1998.

• Dolors Royo, Miguel Valero-García and Antonio González. A Jacobi-based Algorithm for Computing Symmetric Eigenvalues and Eigenvectors in a Two-Dimensional Mesh. In The Sixth Euromicro Workshop on Parallel and Distributing Processing (PDP'98), pp. 463-469, January 1998.

• Enric Fontdecaba, José M. Cela and Juan C. Dürsteler. Parallel Optimisation for Optical Lens Design. In The 3rd International Meeting on Vector and Parallel Processing (VECPAR'98), pp. 657-662, June 1998.

• Enric Fontdecaba, José M. Cela and Juan C. Dürsteler. On the parallelisation of Non-Linear Optimisation Algorithms for Ophthalmical Lens Design. In 4th International Workshop on Applied Parallel Computing in Large Scale Scientific and Industrial Problems (PARA'98), pp. 1-7, June 1998.

• Enric Morancho, José M. Llabería, Angel Olivé and Marta Jiménez. One-Cycle Zero-Offset Loads. In Second IASTED International Conference European Parallel and Distributes Systems (Euro-PDS'98), pp. 87-93, July 1998.

• Enric Morancho, José M. Llabería and Angel Olivé. Split Last-Address Predictor. In IX Jornadas de Paralelismo, pp. 275-282, September 1998.

• Enric Morancho, José M. Llabería and Angel Olivé. Split Last Address Predictor. In The 1998 International Conference on Parallel Architectures and Compilation Techniques (PACT'98), pp. 230-239, October 1998.

• Ernest Artiaga, José I. Navarro, Xavier Martorell and Yolanda Becerra. Experiences on Implementing PARMACS Macros to Run the SPLASH-2 Suite on Multiprocessors. In The Sixth Euromicro Workshop on Parallel and Distributing Processing (PDP'98), pp. 64-69, January 1998.

• Alexandre Farcy, Olivier Temam, Roger Espasa and Toni Juan. Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. In 31st Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-31), pp. 59-68, November 1998.

• Jesús Sánchez and Antonio González. Data Locality Analysis of the SPECfp95. In Workshop on Performance Analysis and its Impact on Design (PAID'98) (held in conjuntion with ISCA'98), pp. 1-7, June 1998.

• Jesús Sánchez and Antonio González. Fast, Flexible and Accurate Data Locality Analysis. In The 1998 International Conference on Parallel Architectures and Compilation Techniques (PACT'98), pp. 124-129, October 1998.

• Jesús Corbal, Roger Espasa and Mateo Valero. Command Vector Memory Systems: High Performance at Low Cost. In IX Jornadas de Paralelismo, pp. 299-306, September 1998.

• Jesús Corbal, Roger Espasa and Mateo Valero. Command-Vector Memory System. In The 1998 International Conference on Parallel Architectures and Compilation Techniques (PACT'98), pp. 68-77, October 1998.

• Joan M. Parcerisa and Antonio González. The Latency Hiding Effectiveness of Decoupled Access/Execute Processors. In 24th EUROMICRO Conference (EUROMICRO'98), pp. 293-300, August 1998.

• Jordi Tubella and Antonio González. Control Speculation in Multithreaded Processors through Dynamic Loop Detection. In The Fourth International Symposium on High-Performance Computer Architecture (HPCA'98), pp. 14-23, January 1998.

• José González and Antonio González. The Potential of Data Value Speculation to Boost ILP. In International Conference on Supercomputing (ICS'1998), pp. 21-28, July 1998.

• José González and Antonio González. Limits of Instruction Level Parallelism with Data Value Speculation. In The 3rd International Meeting on Vector and Parallel Processing (VECPAR'98), pp. 585-598, June 1998.

• Josep-L. Larriba-Pey, Daniel Jiménez, Emely Arraiz, Enric Guinovart and Juan J. Navarro. CC-Radix: Cache Conscious In-core Sorting for Superscalar Workstations. In IX Jornadas de Paralelismo, pp. 259-266, September 1998.

• Luis A. Villa, Roger Espasa and Mateo Valero. A Performance Study of Out-of-order Vector Architectures and Short Registers. In International Conference on Supercomputing (ICS'1998), pp. 37-44, July 1998.

• Luis A. Villa, Roger Espasa and Mateo Valero. Effective Usage of Vector Registers in Decoupled Vector Architectures. In The Sixth Euromicro Workshop on Parallel and Distributing Processing (PDP'98), pp. 495-501, January 1998.

• Luis A. Villa, Roger Espasa and Mateo Valero. Registers Size Influence on Vector Architectures. In The 3rd International Meeting on Vector and Parallel Processing (VECPAR'98), pp. 495-506, June 1998.

• Luis A. Villa, Roger Espasa and Mateo Valero. Rendimiento de una Cache Escalar en una Arquitectura Vectorial Fuera de Orden. In 8th International Conference of Electronics Communications and Computers (CONIELECOMP'98), pp. 230-235, February 1998.

• Marcio M. Fernandes, Josep Llosa and Nigel Topham. Partitioned Schedules for Clustered VLIW Architectures. In 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP'1998), pp. 386-391, March 1998.

• Marta Jiménez, José M. Llabería and Agustín Fernández. Performance Evaluation of Tiling for the Register Level. In The Fourth International Symposium on High-Performance Computer Architecture (HPCA'98), pp. 254-265, January 1998.

• Marta Jiménez, José M. Llabería, Agustín Fernández and Enric Morancho. A General Algorithm for Tiling the Register Level. In International Conference on Supercomputing (ICS'1998), pp. 133-140, July 1998.

• Marta Jiménez, José M. Llabería and Agustín Fernández. Loop Bounds Computation for Multilevel Tiling. In The Sixth Euromicro Workshop on Parallel and Distributing Processing (PDP'98), pp. 445-452, January 1998.

• Marta Jiménez, José M. Llabería and Agustín Fernández. Performance Evaluation of Tiling for the Register Level. In IX Jornadas de Paralelismo, pp. 127-137, September 1998.

• Miguel Valero-García, Antonio González, Luis Díaz de Cerio and Dolors Royo. Divide-and-Conquer Algorithms on Two-Dimensional Meshes. In 4th International Euro-Par Conference (Euro-Par'98), pp. 1051-1056, September 1998.

• Francisca Quintana, Roger Espasa and Mateo Valero. A Case for Merging the ILP and DLP Paradigms. In The Sixth Euromicro Workshop on Parallel and Distributing Processing (PDP'98), pp. 217-224, January 1998.

• Francisca Quintana, Roger Espasa and Mateo Valero. An ISA Comparison between Superscalar and Vector Processors. In The 3rd International Meeting on Vector and Parallel Processing (VECPAR'98), pp. 439-451, June 1998.

• Pedro Marcuello, Antonio González and Jordi Tubella. Speculative Multithreaded Processors. In International Conference on Supercomputing (ICS'1998), pp. 77-84, July 1998.

• Pedro Marcuello and Antonio González. Control and Data Dependence Speculation in Multithreaded Processors. In Workshop on Multithreaded Execution, Architecture and Compilation (held in conjuntion with HPCA-4), pp. 1-8, January 1998.

• Pedro Marcuello and Antonio González. Data Speculative Multithreaded Architecture. In 24th EUROMICRO Conference (EUROMICRO'98), pp. 321-324, August 1998.

• Eleftherios Polychronopoulos, Xavier Martorell, Dimitrios Nikolopoulos, Jesús Labarta, Theodore Papatheodorou and José I. Navarro. Kernel-Level Scheduling for the Nano-Threads Programming Model. In International Conference on Supercomputing (ICS'1998), pp. 337-344, July 1998.

• J.M. Puiatti, C. Piguet, Josep Llosa and E. Sánchez. Low-Power VLIW Processors: A High-Level Evaluation. In Power Driven Microarchitecture Workshop (held in Conjuntion with ISCA'98), pp. 140-144, June 1998.

• J.M. Puiatti, E. Sánchez, C. Piguet and Josep Llosa. VLIW Architectures for Low-Power Processors: A First Evaluation. In 24th European Solid-State Circuits Conference, pp. 436-439, January 1998.

• J.M. Puiatti, E. Sánchez, C. Piguet and Josep Llosa. Low-Power VLIW Processors: A High-Level Evaluation. In 8th International Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS'98), pp. 399-408, October 1998.

• Roger Espasa, Mateo Valero and James E. Smith. Vector Architectures: Past, Present and Future. In International Conference on Supercomputing (ICS'1998), pp. 425-432, July 1998.

• Toni Cortés and Jesús Labarta. PAFS: a new Generation in Cooperative Caching. In International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'98), pp. 267-274, July 1998.