Speculative multithreading (SpMT) is a dynamic parallelization technique that depends on out-of-order execution to achieve speedup. Although studies have generally shown the potential for significant performance gains, there are several perceived problems with the approach.  Software SpMT is regarded as unfeasible due to the expense of creating and joining many short-lived threads on current multiprocessors, whereas hardware SpMT requires novel and expensive architectural support.  In this talk we present our current work on SableSpMT, a software SpMT implementation for Java, and discuss future optimization possibilities that we are currently investigating, including application of purity/escape analysis, support for transactions, and general reduction of thread overhead.

Chris Pickett is a Ph.D. student at McGill University, as part of the Sable Research Group.  He is also an IBM CAS Fellowship student and so spends 4 months out of the year at CAS in Markham.  He is supervised by Clark Verbrugge at McGill and Allan Kielstra at IBM.  He has been working on speculative multithreading since becoming a graduate student in 2002, and as a completely unrelated side project has worked on formal verification of computer game narratives.  Broader research interests include compilers, dynamic optimization, virtual machines, and concurrency.

A task model will be one of the major enhancements added into the up coming OpenMP 3.0 standard. This talk will give the audience a sneak preview of what it looks like, and how users can explore the concept of tasks to take advantage of an ever increasing number of multi-core and multi-threaded machines. Yet, OpenMP is traditionally considered as a thread-based language extension. It will be interesting to see how the idea of a task interacts with the existing OpenMP concepts, such as the thread private variable and OpenMP thread number. Moreover, the demand for high performance does not stop there. It is equally challenging to know how to map the OpenMP threads to the modern hierarchical architecture, such as Power5 system. The real world examples will be used to show how important this is, as thread affinity can affect the performance number as big as 40%.

Dr. Zhang got a PhD. degree from HIT, China in 1995. He worked on HPF and Java compilers as a Research Scientist in NPAC at Syracuse University from 1995. He joined IBM Toronto Lab in 1999. He implemented the major OpenMP 2.0 features in the IBM XL C/C++ and XL Fortran compilers' backend and runtime. He participates in language committee discussions for the OpenMP 2.5 and 3.0 standards as one of the IBM representatives.

Many programs exhibit some high-level parallelism but may not be parallelizable because of the program's size and complexity.  In addition, their parallelism may be dynamic and available with certain inputs only. In this paper we present the design and implementation of {\em speculative co-processing}, which uses an extra processor to speculatively execute likely parallel regions of code.  We show that this speculation improves performance when the parallelism exists.  When there is not parallelism, the program still runs correctly and completes as quickly as the unmodified sequential version.  We show our software-based implementation of speculative co-processing successfully parallelizes two large open-source applications and a scientific library and improves their performance by up to 86\% on a dual-processor PC.  The results demonstrate the importance of the three novel features of speculative co-processing: language support for specifying possible (rather than definitive) program behavior, strong isolation to ensure correctness, and using redundant computation to hide the overhead of run-time monitoring and correctness checking.  

He got his bachelor's degree from Shandong University at 1995 and master's degree from Beijing univeristy at 1999.  After that he enrolled university of Rochester to continue his PhD studies. Now he is working on program localilty optimization and coarse-grain parallization under Professot Chen Ding advising.

The SARC (Scalable computer ARChitecture) european project is defining, on one side, the architecture of the future Chip-Multiprocessors (CMPs), containing a number of main cores, along with hardware accelerators to perform optimized functions. On the other side, such an architecture requires to develop extensions to programming models such as OpenMP and MPI to exploit its specific characteristics. In this project, we are proposing extensions to OpenMP to allow the programmers to give hints to the compiler with respect the placement of the code in the accelerators.
For instance, specific sections of code can be annotated with an attribute indicating the kind of accelerator that would be appropriate to execute them. Given these extra specifications of placement, the task of the compiler is to outline the code affected by the directive and call the appropriate service to the runtime system to execute this task in the accelerator. To achieve this, the compiler has to determine which are the parameters needed by the function n the accelerator and use some run-time system service to transfer them, nd collect the results. In our current prototype developed on the Cell BE rocessor, this is done using the DMA primitives available. We have started coding some small benchmarks, like matrix multiply, using these extensions, and we will show the results of the evaluation in the presentation.

Dr. Martorell received the M.S. and Ph.D. degrees in computer science from the Technical University of Catalunya (UPC) in 1991 and 1999, respectively. Since 1992 he has lectured on operating systems, parallel runtime systems and OS administration. He has been an associate professor in the Computer Architecture Department at UPC since 2001. His research interests cover the areas of operating systems, runtime systems, compilers and applications for high-performance multiprocessor systems. Dr. Martorell has participated in several long-term research projects with other universities and industries, primarily in the framework of the European Union ESPRIT, IST and FET programs. He spent one year working with the BG/L team in the IBM Watson Research Center. He is currently the Manager of the Parallel Programming Models team at the Barcelona Supercomputing center.

In this talk I will describe the design and implementation of the OpenMP and vectorization modules in GCC. The talk will concentrate on the internal architecture and intermediate representation, which could be used in the implementation of automatic parallelization techniques.

Diego Novillo was born in Cordoba, Argentina and holds a PhD in Parallel Computing from the University of Alberta, Canada. He is a Principal Engineer at Red Hat Canada (previously Cygnus), currently working for the compiler group. He has been working on GCC since 1999 and is one of the main architects of GCC's global optimization framework. Diego is a maintainer of various GCC modules including OpenMP, alias analysis and SSA-based optimizers.